The subject invention relates to testing pulse generators and more particularly, to testing pulse generators responsive to address transition in a memory circuit.
Address transition detection has been found to be useful in improving the speed-power product for memories, particularly static random access memories (SRAMs). One of the primary uses of address transition detection is to equalize the voltage on pairs of bit lines just prior to sensing data. An equalization pulse is generated in response to detecting an address transition. While the equalization pulse must be of sufficient duration to equalize the bit lines, it is desirable for the equalization pulse to be as short in duration as possible to minimize access time. Accordingly, for a given memory there is an optimum pulse width for the equalization pulse.
Such optimum pulse width can be estimated with modelling techniques. The actual pulse width produced in a device may differ from that desired. Because it may be a relatively narrow pulse, 10-20 nanoseconds, the design can be quite critical. A slight design or modelling error can result in a pulse so narrow as to not actually equalize the bit lines, or worse, result in no pulse at all. Obviously such a design requires correction before production can be started. Nonetheless, it is still desirable to be able to test other aspects of the memory for design defects so that as many design corrections as possible can be made at the same time. The time from a design correction to a device that can be tested is typically six weeks.
The equalization pulse circuitry is a relatively small portion of the memory. Consequently, to only be able to discover that the equalization pulse circuitry requires a design correction, leaves the vast majority of the device untested. If, however, the equalization pulse is of a longer duration than optimum, the rest of the memory can typically be effectively tested. Other design defects than those of the equalization pulse circuitry can then be corrected. Consequently, the consequences of no pulse or one too short to be able to equalize the bit lines sufficiently to read data are more severe than when the pulse is longer than optimum.